SST25VF016B View Datasheet(PDF) - Microchip Technology
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SST25VF016B Datasheet PDF : 30 Pages
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SST25VF016B
4.4 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF016B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4: DEVICE OPERATION INSTRUCTIONS
Instruction
Description
Op Code Cycle1
Address
Cycle(s)2
Read
Read Memory at 25 MHz 0000 0011b (03H)
3
High-Speed Read Memory at 50 MHz 0000 1011b (0BH)
3
Read
4 KByte Sector- Erase 4 KByte of
Erase3
memory array
0010 0000b (20H)
3
32 KByte Block- Erase 32 KByte block
Erase4
of memory array
0101 0010b (52H)
3
64 KByte Block- Erase 64 KByte block
Erase5
of memory array
1101 1000b (D8H)
3
Chip-Erase
Erase Full Memory Array 0110 0000b (60H) or
0
1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H)
3
AAI-Word-Pro- Auto Address Increment
1010 1101b (ADH)
3
gram6
Programming
RDSR7
Read-Status-Register
0000 0101b (05H)
0
EWSR
Enable-Write-Status-Register 0101b 0000b (50H)
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
WREN
Write-Enable
0000 0110b (06H)
0
WRDI
RDID8
Write-Disable
Read-ID
0000 0100b (04H)
0
1001 0000b (90H) or
3
1010 1011b (ABH)
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
EBSY
Enable SO to output RY/BY# 0111 0000b (70H)
0
status during AAI program-
ming
DBSY
Disable SO as RY/BY#
1000 0000b (80H)
0
status during AAI program-
ming
Dummy
Cycle(s)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
Cycle(s)
1 to
1 to
0
0
0
0
1
2 to
1 to
0
1
0
0
1 to
3 to
0
0
Maximum
Frequency
25 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
DS20005044C-page 8
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2015 Microchip Technology Inc.
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