MCP9800 View Datasheet(PDF) - Microchip Technology
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MCP9800 Datasheet PDF : 42 Pages
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4.0 SERIAL COMMUNICATION
4.1 2-Wire SMBus/Standard Mode
I2C™ Protocol-Compatible
Interface
The MCP9800/1/2/3 serial clock input (SCL) and the
bidirectional serial data line (SDA) form a 2-wire
bidirectional SMBus/Standard mode I2C compatible
communication port (refer to the Digital Input/Output
Pin Characteristics Table and Serial Interface
Timing Specifications Table).
The following bus protocol has been defined:
TABLE 4-1: MCP9800 SERIAL BUS
PROTOCOL DESCRIPTIONS
Term
Description
Master
The device that controls the serial bus,
typically a microcontroller.
Slave
The device addressed by the master,
such as the MCP9800/1/2/3.
Transmitter Device sending data to the bus.
Receiver Device receiving data from the bus.
Start
A unique signal from master to initiate
serial interface with a slave.
Stop
A unique signal from the master to
terminate serial interface from a slave.
Read/Write A read or write to the MCP9800/1/2/3
registers.
ACK
A receiver Acknowledges (ACK) the
reception of each byte by polling the
bus.
NAK
A receiver Not-Acknowledges (NAK) or
releases the bus to show End-of-Data
(EOD).
Busy
Communication is not possible
because the bus is in use.
Not Busy The bus is in the Idle state, both SDA
and SCL remain high.
Data Valid
SDA must remain stable before SCL
becomes high in order for a data bit to
be considered valid. During normal
data transfers, SDA only changes state
while SCL is low.
MCP9800/1/2/3
4.1.1 DATA TRANSFER
Data transfers are initiated by a Start condition (Start),
followed by a 7-bit device address and a read/write bit.
An Acknowledge (ACK) from the slave confirms the
reception of each byte. Each access must be
terminated by a Stop condition (Stop).
Repeated communication is initiated after tB-FREE.
This device does not support sequential register read/
write. Each register needs to be addressed using the
Register Pointer.
This device supports the Receive Protocol. The
register can be specified using the pointer for the initial
read. Each repeated read or receive begins with a Start
condition and address byte. The MCP9800/1/2/3
retains the previously selected register. Therefore, it
outputs data from the previously-specified register
(repeated pointer specification is not necessary).
4.1.2 MASTER/SLAVE
The bus is controlled by a master device (typically a
microcontroller) that controls the bus access and
generates the Start and Stop conditions. The
MCP9800/1/2/3 is a slave device and does not control
other devices in the bus. Both master and slave
devices can operate as either transmitter or receiver.
However, the master device determines which mode is
activated.
4.1.3 START/STOP CONDITION
A high-to-low transition of the SDA line (while SCL is
high) is the Start condition. All data transfers must be
preceded by a Start condition from the master. If a Start
condition is generated during data transfer, the
MCP9800/1/2/3 resets and accepts the new Start
condition.
A low-to-high transition of the SDA line (while SCL is
high) signifies a Stop condition. If a Stop condition is
introduced during data transmission, the MCP9800/1/
2/3 releases the bus. All data transfers are ended by a
Stop condition from the master.
4.1.4 ADDRESS BYTE
Following the Start condition, the host must transmit an
8-bit address byte to the MCP9800/1/2/3. The address
for the MCP9800 Temperature Sensor is
‘1001,A2,A1,A0’ in binary, where the A2, A1 and A0
bits are set externally by connecting the corresponding
pins to VDD ‘1’ or GND ‘0’. The 7-bit address
transmitted in the serial bit stream must match the
selected address for the MCP9800/1/2/3 to respond
with an ACK. Bit 8 in the address byte is a read/write
bit. Setting this bit to ‘1’ commands a read operation,
while ‘0’ commands a write operation (see Figure 4-1).
2010 Microchip Technology Inc.
DS21909D-page 11
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