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MCP9800A3 View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
MCP9800A3
Microchip
Microchip Technology Microchip
MCP9800A3 Datasheet PDF : 42 Pages
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MCP9800/1/2/3
Address Byte
SCL
12345678 9
SDA
Start
A
C
1 0 0 1 A2 A1 A0
K
Address
Code
Slave
Address
R/W
PIC18FXXXX Response
FIGURE 4-1:
Device Addressing.
4.1.5 DATA VALID
After the Start condition, each bit of data in
transmission needs to be settled for a time specified by
tSU-DATA before SCL toggles from low-to-high (see
“Serial Interface Timing Specifications” on Page 5).
4.1.6 ACKNOWLEDGE (ACK)
Each receiving device, when addressed, is obliged to
generate an ACK bit after the reception of each byte.
The master device must generate an extra clock pulse
for ACK to be recognized.
The acknowledging device pulls down the SDA line for
tSU-DATA before the low-to-high transition of SCL from
the master. SDA also needs to remain pulled down for
tH-DATA after a high-to-low transition of SCL.
During read, the master must signal an End-of-Data
(EOD) to the slave by not generating an ACK bit (NAK)
once the last bit has been clocked out of the slave. In
this case, the slave will leave the data line released to
enable the master to generate the Stop condition.
DS21909D-page 12
2010 Microchip Technology Inc.

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