MT8MTF51264HRZ View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT8MTF51264HRZ

1.35V DDR3L-RS SDRAM SODIMM

Micron Technology 

4GB (x64, SR) 204-Pin DDR3L-RS SODIMM

Pin Descriptions

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 6: Pin Descriptions

Symbol

Ax

BAx

CKx,

CKx#

CKEx

DMx

ODTx

Par_In

RAS#, CAS#, WE#

RESET#

Sx#

SAx

SCL

CBx

DQx

DQSx,

DQSx#

Type

Input

Input

Input

Input

Input

Input

Input

Input

Input

(LVCMOS)

Input

Input

Input

I/O

I/O

I/O

Description

Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments table for density-specific ad-

dressing information.

Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I2C bus.

Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I2C bus.

Check bits: Used for system error detection and correction.

Data input/output: Bidirectional data bus.

Data strobe: Differential data strobes. Output with read data; edge-aligned with

read data; input with write data; center-aligned with write data.

PDF: 09005aef84fc0fd3

mtf8c512x64hz_g0_h0.pdf - Rev. D 5/13 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2012 Micron Technology, Inc. All rights reserved.

Share Link: