AT32UC3A3128(2009) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT32UC3A3128
(Rev.:2009)

AVR®32 32-Bit Microcontroller

Atmel Corporation 

Figure 5-1. Overview of the AVR32UC CPU

AT32UC3A3

OCD

system

Power/

Reset

control

AVR32UC CPU pipeline

MPU

Instruction memory controller

High Speed Bus master

Data memory controller

High

Speed

Bus

master

High CPU Local

Speed

Bus

Bus slave master

5.3.1

Pipeline Overview

AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-

tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic

(ALU) section, one multiply (MUL) section, and one load/store (LS) section.

Instructions are issued and complete in order. Certain operations require several clock cycles to

complete, and in this case, the instruction resides in the ID and EX stages for the required num-

ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is

required, and no data dependencies can arise in the pipeline.

Figure 5-2 on page 21 shows an overview of the AVR32UC pipeline stages.

20

32072A–AVR32–03/09

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