81C51SL-AH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
81C51SL-AH Datasheet PDF : 23 Pages
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8XC51SL LOW VOLTAGE 8XC51SL
Low Voltage 8XC51SL DC Characteristics (Over Operating Conditions)
Symbol
Parameter
Min
Max
Units
ITL
Logical 1 to 0 Transition
Current QB(2) Pins
b650
mA
ICC
Power Supply Current
Active Mode at 16 MHz
Idle Mode at 16 MHz
Power-Down Mode
25
mA
10
mA
175
mA
Test Conditions
VIN e 1 5V
NOTES
1 Bidirectional (BP) pins include P27 LED4 P30 SIF00 P31 SIF01 P33 SIF10 P36 SIF11 MEMCSL PCDB0 –7 and
ADB0 – 7
2 Quasi-bidirectional (QB) pins include P20–6 A8–A14 P32 INT0 P34 T0 P36 WRL P37 RDL and P10– 7 A0 –7
3 Pure input pins include LOADREN EAL A0 A1 CSL RDL WRL RST AIN0– 3 and XTAL1
AC Characteristics
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has three or five characters The
first character is always ‘‘T’’ (for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal Table 3 lists the characters and their mean-
ings
Example
TAVLL e Time for Address Valid to ALE Low
TLLPL e Time for ALE Low to PSEN Low
Char
A
C
D
H
I
L
P
Q
R
T
V
W
X
Z
Table 3 AC Symbol Characters
Meaning
Address
Clock
Input Data
Logic Level HIGH
Instruction (Program Memory Contents)
Logic Level LOW or ALE
PSENL
Output Data
RDL Signal
Time
Valid
WRL Signal
No Longer a Valid Logic Level
Float
HOST-INTERFACE TIMING
All Outputs Loaded with 50 pF
Symbol
Parameter
Min
Max
Units
TAR
CSL A0 A1 Setup to RD Low
0
ns
TRA
CSL A0 A1 Hold after RDL High
0
ns
TAD
CSL A0 A1 to Data Out Delay
50
ns
TAW
CSL A0 A1 Setup to WRL Low
0
ns
TWA
CSL A0 A1 Hold after WRL High
10
ns
TDW
Data Setup to WRL High
60
ns
TWD
Data Hold after WRL High
5
ns
TWW
Minimum Pulse Width of WRL
50
ns
TRR
RDL Pulse Width
50
ns
TRD
RDL Low to Data Out Delay
50
ns
TDF
RDL High to Data Float Delay
50
ns
13
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