KU80C51SL-AL View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
KU80C51SL-AL Datasheet PDF : 23 Pages
| |||
8XC51SL LOW VOLTAGE 8XC51SL
Sample Window Begins when the sample capaci-
tor is attached to a selected channel and ends when
the sample capacitor is disconnected from the se-
lected channel
Successive Approximation An A D conversion
method which uses a binary search to arrive at the
best digital representation of an analog input
Temperature Coefficients Change in the stated
variable per degree centrigrade temperature
change Temperature coefficients are added to the
typical values of a specification to see the effect of
temperature drift
Terminal Based Characteristic An actual charac-
teristic which has been rotated and translated to re-
move zero offset and full scale error
VCC Rejection Attenuation of noise on the VCC
line to the A D converter
Zero Offset The difference between the expected
and actual input voltage corresponding to the first
code transition
DATA SHEET REVISION SUMMARY
The following differences exist between this data
sheet (272271-002) and the previous version
(272271-001)
1 Data sheet status changed from ‘‘Product Pre-
view’’ to ‘‘Advance Information’’
2 Title page item number three describing the glob-
al interrupt enable change was removed
3 Title page item number two was corrected to read
‘‘ was added in configuration register 1 ’’
4 In the 8XC51SL DC Characteristics section
The VOH test condition (IOH) changed from
b0 8 mA to b60 mA
The VOH1 test condition (IOH) changed from
b4 0 mA to b2 0 mA
VOH2 was added
The XTAL1 and EAL pins were added to the ILI
spec
The ITL spec changed from b650 mA to b1 mA
The ICC idle spec changed from 10 mA to 15 mA
The ICC Power Down spec changed from 100 mA
to TBD
5 In the Low Voltage 8XC51SL DC Characteristics
section
The VOH spec changed from 2 4V to VCC b0 7
The VOH test condition (IOH) changed from
b0 8 mA to b60 mA
VOH2 was added
Pins were clarified in the ILI spec
The ITL test condition (VIN) was changed from
TBD to 1 5V
The ICC Power Down spec changed from 100 mA
to 175 mA
6 The load capacitance for all timing tables was
changed to 50 pF
7 In the Host Interface Timing Section TWD
changed from 0 ns to 5 ns
8 The External Memory Timing table changed as
follows
Spec
Old
New
TLLIV
4TCLCL-50
4TCLCL-100
TPLIV
3TCLCL-50
3TCLCL-105
TPXIZ
TCLCL-15
TCLCL-25
TAVIV
5TCLCL-50
5TCLCL-105
TRLDV
5TCLCL-50
5TCLCL-100
TLLDV
8TCLCL-50
8TCLCL-100
TAVDV
9TCLCL-50
9TCLCL-100
TMVDV
9TCLCL-50
Removed
TMVIV
5TCLCL-50
Removed
9 In Figures 5 and 7 the MEMCSL waveforms were
removed
10 Clarification was added in the Programming Al-
gorithm section
11 In the A D Converter Specifications section the
minimum resolution was changed from 256 lev-
els to 255 levels
12 The Data Sheet Revision Summary was added
23
Share Link: 