KU80C51SL-AH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

KU80C51SL-AH

8XC51SL/LOW VOLTAGE 8XC51SL KEYBOARD CONTROLLER

Intel 

8XC51SL LOW VOLTAGE 8XC51SL

PORT STRUCTURES AND

OPERATION

All three 51SL ports are bidirectional Each consists

of a latch (Special Function Registers P1 through

P3) an output driver and an input buffer Port 0 of

the 51SL CPU does not connect to the package

pins It is used internally to drive the keyboard scan

logic

The output drivers of ports 1 and 2 can be used in

accesses to external memory The 51SL provides

the LOADREN signal to facilitate external memory

interfaces When the LOADREN signal is high Port

1 outputs the low byte of the external memory ad-

dress If LOADREN is tied low then the Port 1 sig-

nals continue to emit the P1 SFR content Port 2

outputs the upper seven bits of the high byte of the

external address when the address is 15 bits wide

and either EAL is tied low or EAL is tied high and Bit

0 (ADDREN) of configuration register 1 is set Other-

wise the Port 2 pins continue to emit the P2 SFR

content

I O Configurations

All port pins with the exception of P27 LED4

P30 SIF00 P31 SIF01 P33 SIF10 and P35 SIF11

have fixed internal pullups and therefore are called

‘‘quasi-bidirectional ports’’ When configured as in-

puts the pins are pulled high by the pullups and will

source current when externally pulled low

During a 15-bit external program memory access

Port 2 outputs the high address byte In the 80C51

the Port 2 drivers use the strong pullup during the

entire time that they are emitting a ‘‘1’’ on a Port 2

bit In this instance the 80C51 weak quasi-bidirec-

tional pullup condition that normally occurs after two

oscillator periods does not occur Port 1 and Port 2

of the 51SL emulate the quasi-bidirectional pullup

condition during program memory access not this

extended strong pullup condition

POWER MANAGEMENT

The 51SL uses low power CHMOS and provides for

two further power savings modes available when in-

active Idle mode typically between keystrokes and

Power Down mode upon command from the host A

four channel eight-bit A D converter is also includ-

ed for power management (i e battery voltage tem-

perature monitoring etc )

Idle Mode

Idle mode is initiated by an instruction that sets the

PCON 0 bit (SFR address 87H) in the 51SL In Idle

mode the internal clock signal to the 51SL CPU is

gated off but not to the interrupt timer and Serial

Port functions The 51SL status is preserved in its

entirety the Stack Pointer Program Counter Pro-

gram Status Word Accumulator and all other regis-

ters maintain their data The port pins hold the logic

levels they had when Idle mode was activated ALE

and PSENL are held high If an A D conversion is in

process when Idle mode is entered any conversion

results may contain erroneous data Idle mode is ex-

ited via a hardware reset or an enable interrupt

Power Down Mode

Power Down mode is initiated by an instruction that

sets bit PCON 1 in the 51SL CPU When the 51SL

enters Power Down mode all internal clocks includ-

ing the 51SL core clock are turned off If an external

crystal is used the internal oscillator is turned off

MEMCSL the external memory select signal goes

inactive unless it is configured as a general purpose

I O (i e unless bit 3 of configuration register 1 is a

‘‘1’’) ALE and PSENL are both forced low RAM

contents are preserved

Power Down mode can only be exited via a reset

This reset may occur either from the RST pin or an

internally generated reset See the 51SL Hardware

Description (Order No 272268) for a detailed de-

scription of this reset

HOST INTERFACE

The 51SL host interface is functionally compatible

with the 8042 style UPI interface It consists of the

PCDB0 – 7 data bus the RDL WRL A0 and CSL

control signals and the Keyboard Status register

Input Data register and Output Data register In ad-

dition a second address line A1 has been added to

decode a second set of registers for power manage-

ment functions These registers are identical to the

keyboard registers The host interface also includes

a PCOBF interrupt GATEA20 and host reset (RCL)

outputs Two additional OBF signals AUXOBF1 and

AUXOBF2 are available through firmware configura-

tion of P34 T0 and P37 RDL respectively

9

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