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STM8S105S6(2015) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STM8S105S6 Datasheet PDF : 121 Pages
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STM8S105x4/6
Product overview
4.14.2
4.14.3
LIN slave mode
ï‚· Autonomous header handling - one single interrupt per valid message header
 Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%
ï‚· Synch delimiter checking
ï‚· 11-bit LIN synch break detection - break detection always active
ï‚· Parity check on the LIN identifier field
ï‚· LIN error management
ï‚· Hot plugging support
SPI
ï‚· Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
ï‚· Full duplex synchronous transfers
ï‚· Simplex synchronous transfers on two lines with a possible bidirectional data line
ï‚· Master or slave operation - selectable by hardware or software
ï‚· CRC calculation
ï‚· 1 byte Tx and Rx buffer
ï‚· Slave/master selection input pin
I2C
 I²C master features:
– Clock generation
– Start and stop generation
 I²C slave features:
– Programmable I2C address detection
– Stop bit detection
ï‚· Generation and detection of 7-bit/10-bit addressing and general call
ï‚· Supports different communication speeds:
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
DocID14771 Rev 15
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