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STM8S105S6B6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STM8S105S6B6 Datasheet PDF : 127 Pages
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STM8S105xx
3
Block diagram
Figure 1: STM8S105xx access line block diagram
Block diagram
Reset
Reset block
Reset
POR
BOR
Clock controller
Detector
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Single wire
debug interf.
Master/slave
autosynchro
LIN master
SPI emul.
400 Kbit/s
8 Mbit/s
Up to 10 channels
1/2/4 kHz
beep
Clock to peripherals and core
STM8 core
Debug/SWIM
UART2
I2C
SPI
Window WDG
Independent WDG
Up to 32 Kbytes
program Flash
1 Kbytes
data EEPROM
Up to 2 Kbytes
RAM
Boot ROM
16-bit advanced control
timer (TIM1)
ADC1
Beeper
16-bit general purpose
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
AWU timer
Up to
4 CAPCOM
channels +3
complementary
outputs
Up to
5 CAPCOM
channels
DocID14771 Rev 9
11/127

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