NXP Semiconductors
HEF4046B
Phase-locked loop
Table 6. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns.
Symbol Parameter
Conditions
f/f
relative frequency for VCO see Figure 13 and 14
variation
R1 > 10 k
VDD
5V
Min Typ
-
0.50
R1 > 400 k
10 V -
0.25
R1 = M
15 V -
0.25
duty factor
VCO _OUT output
5V -
50
10 V -
50
15 V -
50
Rin
input resistance
for pin VCO_IN
10
Source follower
Voffset offset voltage
RL = 10 k; VCO_IN at 0.5VDD
5 V [2] -
1.7
10 V -
2.0
15 V -
2.1
RL = 50 k; VCO_IN at 0.5VDD
5V -
1.5
10 V -
1.7
15 V -
1.8
f/f
relative frequency
VCO output; RL > 50 k; see Figure 13 5 V
-
0.3
variation
10 V -
1.0
15 V -
1.3
Zener diode
VZ
working voltage
IZ = 50 A
-
Rdyn
dynamic resistance For internal Zener diode; IZ = 1 mA
-
-
7.3
-
25
[1] Over the recommended component range.
[2] The offset voltage is equal to the input voltage on pin VCO_IN minus the output voltage on pin SF_OUT.
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
% Hz
% Hz
% Hz
%
%
%
M
V
V
V
V
V
V
%
%
%
V
11. Design information
Table 7. Design information
Test
VCO adjusts with no signal on SIG_IN
Phase angle between SIG_IN and COMP_IN
Locks on harmonics of center frequency
Signal input noise rejection
Lock frequency range (2fL)
Capture frequency range (2fc)
Center frequency (f0)
Using phase comparator 1
Using phase comparator 2
VCO in PLL system adjusts
to center frequency (f0)
90 at center frequency (f0),
approaching 0 and 180 at the
ends of the lock range (2fL)
yes
VCO in PLL system adjusts to
minimum frequency (fmin)
always 0 in lock
(positive-going edges)
no
high
low
the frequency range of the input signal on which the loop will stay locked if it
was initially in lock; 2fL = full VCO frequency range = fmax fmin
the frequency range of the input signal on which the loop will lock if it was
initially out of lock
depends on low-pass
filter characteristics; 2fc < 2fL
2fc = 2fL
the frequency of the VCO when VCO_IN at 0.5VDD
HEF4046B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
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