PCA9617ADPJ View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9617ADPJ Datasheet PDF : 23 Pages
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NXP Semiconductors
PCA9617A
Level translating Fm+ I2C-bus repeater
B-side RC should not be less than 67.5 ns because shorter RCs increase the turnaround
bounce when the B-side transitions from being externally driven to pulled down by its
offset buffer.
Please see Application Note AN255, “I2C/SMBus Repeaters, Hubs and Expanders” for
additional information on sizing resistors and precautions when using more than one
PCA9617A in a system or using the PCA9617A in conjunction with other bus buffers.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at
1000 kHz. Master devices can be placed on either bus.
PCA9617A
Product data sheet
3.3 V
1.2 V
1.4 kΩ
SDA
SCL
BUS
MASTER
1000 kHz
1.4 kΩ
VCC(B)
SDAB
SCLB
1.4 kΩ
VCC(A)
SDAA
SCLA
PCA9617A
EN
1.4 kΩ
SDA
SCL
SLAVE
1000 kHz
bus B
Fig 4. Typical application
bus A
002aag653
The PCA9617A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.8 V to 5.5 V bus voltages and 2.2 V to 5.5 V bus voltages.
When port A of the PCA9617A is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9617A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus master in Figure 4 were to write to the slave through the PCA9617A, waveforms
shown in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus
transmission except that the HIGH level may be as low as 0.8 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
The internal comparator requires that 0.4 VCC(A) be less than or equal to VCC(B) 0.8 V
for the device to operate. Since A port is 5 V tolerant, the VCC(A) can be lowered to support
device spectrum while still supporting 5 V signals on the A port.
On the B bus side of the PCA9617A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9617A. After the eighth clock pulse, the data line
will be pulled to the VOL of the slave device which is very close to ground in this example.
At the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9617A for a short delay while the A bus side rises above 0.3VCC(A) then it continues
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
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