CY7C1381D-133BZC(2004) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1381D-133BZC Datasheet PDF : 29 Pages
| |||
PRELIMINARY
CY7C1381D
CY7C1383D
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Truth Table [ 3, 4, 5, 6, 7]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
80
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Cycle Description
Deselected Cycle,
Power-down
ADDRESS
Used CE1 CE2 CE3 ZZ
None
H X XL
ADSP
X
ADSC ADV WRITE OE CLK DQ
L
X
X
X L-H Tri-State
Deselected Cycle,
Power-down
None
L L XL
L
X
X
X
X L-H Tri-State
Deselected Cycle,
Power-down
None
L X HL
L
X
X
X
X L-H Tri-State
Deselected Cycle,
Power-down
None
L L XL
H
L
X
X
X L-H Tri-State
Deselected Cycle,
Power-down
None
X X XL
H
L
X
X
X L-H Tri-State
Sleep Mode, Power-down
None
X X XH
X
X
X
X
X X Tri-State
Read Cycle, Begin Burst
External L H L L
L
X
X
X
L L-H Q
Read Cycle, Begin Burst
External L H L L
L
X
X
X
H L-H Tri-State
Write Cycle, Begin Burst
External L H L L
H
L
X
L
X L-H D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05544 Rev. *A
Page 8 of 29
Share Link: 