KSZ9021RL View Datasheet(PDF) - Micrel

Part Name

Description

Manufacturer

KSZ9021RL

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9021RL/RN

Pin Number

56

Pin Name

RESET_N

Type(1)

Ipu

57

LDO_O

O

58

AVDDL_PLL

P

59

XO

O

60

XI

I

61

AVDDH

P

62

ISET

I/O

63

64

E-PAD

AGNDH_BG

Gnd

AVDDH

P

E-PAD

Gnd

Note:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input with internal pull-up.

Ipu/O = Input with internal pull-up / Output.

Pin Function

Chip Reset (active low)

Hardware pin configurations are strapped-in at the de-assertion (rising edge) of

RESET_N. See “Strapping Options” section for more details.

On-chip 1.2V LDO Controller Output

This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the

chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it

can be left floating.

1.2V analog VDD for PLL

25MHz Crystal feedback

This pin is a no connect if oscillator or external clock source is used.

Crystal / Oscillator / External Clock Input

25MHz ±50ppm tolerance

3.3V analog VDD

Set transmit output level

Connect a 4.99KΩ 1% resistor to ground on this pin.

Analog ground

3.3V analog VDD

Exposed Pad on bottom of chip

Connect E-PAD to ground.

February 13, 2014

13

Revision 1.2

Share Link: