KSZ9021RL View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
KSZ9021RL Datasheet PDF : 59 Pages
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Micrel, Inc.
KSZ9021RL/RN
RGMII Pad Skew Registers
Pad skew registers are available for all RGMII pins (clocks, control signals, and data bits) to provide programming options
to adjust or correct the timing relationship for each RGMII pin. Because RGMII is a source-synchronous bus interface, the
timing relationship needs to be maintained only within the RGMII pin’s respective timing group.
• RGMII transmit timing group pins:
GTX_CLK, TX_EN, TXD[3:0]
• RGMII receive timing group pins:
RX_CLK, RX_DV, RXD[3:0]
The following three registers located at Extended Registers 260 (104h), 261 (105h), and 262 (106h) are provided for pad
skew programming.
Address
Name
Description
Register 260 (104h) – RGMII Clock and Control Pad Skew
260.15:12 rxc_pad_skew RGMII RXC PAD Skew Control (0.12ns/step)
260.11:8
260.7:4
rxdv_pad_skew
txc_pad_skew
RGMII RX_CTL PAD Skew Control
(0.12ns/step)
RGMII TXC PAD Skew Control (0.12ns/step)
260.3:0
txen_pad_skew RGMII TX_CTL PAD Skew Control
(0.12ns/step)
Register 261 (105h) – RGMII RX Data Pad Skew
261.15:12 rxd3_pad_skew RGMII RXD3 PAD Skew Control (0.12ns/step)
261.11:8
rxd2_pad_skew RGMII RXD2 PAD Skew Control (0.12ns/step)
261.7:4
rxd1_pad_skew RGMII RXD1 PAD Skew Control (0.12ns/step)
261.3:0
rxd0_pad_skew RGMII RXD0 PAD Skew Control (0.12ns/step)
Register 262 (106h) – RGMII TX Data Pad Skew
262.15:12 txd3_pad_skew RGMII TXD3 PAD Skew Control (0.12ns/step)
262.11:8
txd2_pad_skew RGMII TXD2 PAD Skew Control (0.12ns/step)
262.7:4
txd1_pad_skew RGMII TXD1 PAD Skew Control (0.12ns/step)
262.3:0
txd0_pad_skew RGMII TXD0 PAD Skew Control (0.12ns/step)
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
Table 4. RGMII Pad Skew Registers
The RGMII clocks, control signals, and data bits have 4-bit skew settings.
Each register bit is approximately a 0.12ns step change. A single-bit decrement decreases the delay by approximately
0.12ns, while a single-bit increment increases the delay by approximately 0.12ns.
The following table lists the approximate absolute delay for each pad skew (value) setting.
February 13, 2014
30
Revision 1.2
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