Micrel, Inc.
KSZ9021RL/RN
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ9021RL/RN device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
DVDDH
KSZ9021RL/RN
RESET_N
D1
C 10uF
R 10K
D2
CPU/FPGA
RST_OUT_n
D1, D2: 1N4148
Figure 10. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Reference Circuits – LED Strap-in Pins
The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in the
following figure.
DVDDH
Pull-up
10ΚΩ
220Ω
KSZ9021RL/RN
LED pin
Pull-down
KSZ9021RL/RN
LED pin
DVDDH
220Ω
1ΚΩ
February 13, 2014
Figure 11. Reference Circuits for LED Strapping Pins
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Revision 1.2