MAX4748 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX4748 Datasheet PDF : 15 Pages
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50Ω Low-Voltage, Quad SPST/Dual SPDT Analog
Switches in UCSP
Test Circuits/Timing Diagrams (continued)
MAX4747–
MAX4750
VN_
NO_
OR NC_
V+
V+
COM_
LOGIC
INPUT
IN_
GND
RL
300Ω
VOUT
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL
VOUT = VN_ ( RL + RON )
Figure 2. Switching Time
LOGIC VIH
INPUT
VIL
SWITCH
OUTPUT
0
tr < 5ns
tf < 5ns
50%
tOFF
VOUT
0.9 x VOUT
0.9 x VOUT
tON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4749
V+
VN_
NO_
NC_
V+
COM_
COM_
IN_
LOGIC
INPUT
IN_
GND
VOUT2
RL2
300Ω
CL2
35pF
VOUT1
RL1
CL1
300Ω
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval
LOGIC VIH
INPUT
VIL
SWITCH
OUTPUT 1
(VOUT1) 0
SWITCH
OUTPUT 2
(VOUT2)
0
tr < 5ns
tf < 5ns
50%
0.9 x V0UT1
0.9 x VOUT2
tBBM
tBBM
MAX4747–
MAX4750
VGEN
RGEN
NC_
OR NO_
GND
V+
V+
COM
IN_
VILTO VIH
Figure 4. Charge Injection
VOUT
CL
1nF
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
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