ADP3191JRUZ-RL View Datasheet(PDF) - ON Semiconductor
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ADP3191JRUZ-RL Datasheet PDF : 28 Pages
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The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor.
The current information is then given as the difference of
CSREF − CSCOMP. This difference signal is used internally to
offset the VID DAC for voltage positioning and as a differential
input for the current-limit comparator.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors, so it can be made
extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of
output current, a signal proportional to the total output current at
the CSCOMP pin can be scaled to equal the droop impedance of
the regulator multiplied by the output current. This droop voltage
is then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input voltage
directly to tell the error amplifier where the output voltage should
be. This differs from previous implementations and allows
enhanced feed-forward response.
CURRENT-CONTROL MODE AND
THERMAL BALANCE
The ADP3191/ADP3191A have individual inputs for each phase,
which are used for monitoring the current in each phase. This
information is combined with an internal ramp to create a
current balancing feedback system, which has been optimized
for initial current balance accuracy and dynamic thermal
balancing during operation. This current balance information
is independent of the average output current information used
for positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed-forward control for changes in the supply.
A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the Application Information section.
ADP3191
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance, such as
when one phase has better cooling and can support higher
currents. Resistor RSW1 through Resistor RSW4 (see the typical
application circuit in Figure 9) can be used for adjusting
thermal balance. It is best to have the ability to add these resistors
during the initial design, so make sure that placeholders are
provided in the layout.
To increase the current in any given phase, make RSW for this
phase larger (make RSW = 0 for the hottest phase, and do not
change during balancing). Increasing RSW to only 500 Ω makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor (RB)B and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RBB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect
to the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current-limit latch-off
time. In UVLO, or when EN is a logic low, the DELAY pin is held
at ground. After the UVLO threshold is reached and EN is a logic
high, the DELAY capacitor is charged with an internal 20 μA
current source. The output voltage follows the ramping voltage on
the DELAY pin, limiting the inrush current. The soft start time
depends on the value of the VID DAC and CDLY, with a secondary
effect from RDLY. Refer to the Application Information section for
detailed information on setting CDLY.
If EN is taken low or if VCC drops below UVLO, the DELAY
capacitor is reset to ground to be ready for another soft start
cycle. Figure 7 shows a typical soft start sequence for the
ADP3191/ADP3191A.
Rev. 0 | Page 9 of 28
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