AD1893JN View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD1893JN

Low Cost SamplePort® 16-Bit Stereo Asynchronous Sample Rate Converter

Analog Devices 

AD1893

PIN CONFIGURATIONS

DIP

LQFP

XTAL_O 1

XTAL_I 2

SERIAL IN

28 SETSLW

27 PWRDWN

DATA_I 3

BCLK_I 4

WCLK_I 5

LR_I 6

VDD 7

GND 8

NC 9

BKPOL_I 10

MODE0_I 11

MODE1_I 12

SERIAL OUT

ACCUM

MULT

FIFO

COEF ROM

26 BCLK_O

25 WCLK_O

24 LR_O

23 DATA_O

22 VDD

21 GND

20 NC

19 BKPOL_O

18 MODE0_O

17 MODE1_O

NC 1

BCLK_I 2

WCLK_I 3

LR_I 4

NC 5

VDD 6

GND 7

NC 8

BKPOL_I 9

MODE0_I 10

NC 11

44 43 42 41 40 39 38 37 36 35 34

AD1893

SERIAL IN

SERIAL OUT

ACCUM

MULT

FIFO

COEF ROM

CLOCK

TRACKING

33 NC

32 WCLK_O

31 LR_O

30 DATA_O

29 NC

28 VDD

27 GND

26 NC

25 BKPOL_O

24 MODE0_O

23 NC

RESET 13

GND 14

CLOCK

TRACKING

NC = NO CONNECT

AD1893 PIN LIST

AD1893

16 MUTE_O

15 MUTE_I

12 13 14 15 16 17 18 19 20 21 22

NC = NO CONNECT

Serial Input Interface

Pin Name DIP LQFP I/O Description

DATA_I 3

BCLK_I 4

WCLK_I 5

LR_I

6

43 I Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per

channel.

2

I Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.

3

I Word clock input for input data. This input is rising edge sensitive. (Not required in LR input

data clock triggered modes.)

4

I Left/right clock input for input data. Must run continuously.

Serial Output Interface

Pin Name DIP LQFP I/O Description

DATA_O 23 30

O Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per

channel.

BCLK_O 26 35

WCLK_O 25 32

LR_O

24 31

I Bit clock input for output data. Need not run continuously; may be gated or used in a burst

fashion.

I Word clock input for output data. This input is rising edge sensitive. (Not required in LR output

data clock triggered modes.)

I Left/right clock input for output data. Must run continuously.

Input Control Signals

Pin Name DIP LQFP I/O Description

BKPOL_I 10 9

I Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:

Inverted mode. Input data is sampled on falling edges of BCLK_I.

MODE0_I 11 10

I Serial mode zero control for input port.

MODE1_I 12 13

I Serial mode one control for input port.

MODE0_I

0

0

1

MODE1_I

0

Left-justified, no MSB delay, LR_I clock triggered.

1

Left-justified, MSB delay, LR_I clock triggered.

0

Right-justified, MSB delayed 16 bit clock periods from LR_I transition.

1

1

WCLK_I triggered, no MSB delay.

REV. A

–5–

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