AD1893JN View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD1893JN

Low Cost SamplePort® 16-Bit Stereo Asynchronous Sample Rate Converter

Analog Devices 

AD1893

Output Control Signals

Pin Name DIP LQFP I/O Description

BKPOL_O 19 25

I Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed

on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on

rising.

MODE0_O 18 24

I Serial mode zero control for output port.

MODE1_O 17 21

I Serial mode one control for output port.

MODE0_O

0

0

1

1

MODE1_O

0

Left-justified, no MSB delay, LR_O clock triggered.

1

Left-justified, MSB delay, LR_O clock triggered.

0

Right-justified, MSB delayed 16 bit clock periods from LR_O transition.

1

WCLK_O triggered, no MSB delay.

Miscellaneous

Pin Name DIP LQFP

I/O Description

XTAL_O 1

40

XTAL_I 2

42

RESET 13 14

O Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies

(FS word rates) from 8 kHz to 56 kHz.

I Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies

(FS word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator

with an external clock source.

I Active LO reset. Set HI for normal chip operation.

MUTE_O 16 20

O Mute output. HI indicates that data is not currently valid due to read and write FIFO

memory pointer overlap. LO indicates normal operation.

MUTE_I 15 18

SETLSLW 28 38

I Mute input. HI mutes the serial output to zeros (midscale). Normally connected to

MUTE_O. Reset LO for normal operation.

I Settle slowly to changes in sample rates. HI: Slow-settling mode (≈800 ms). Less sensitive

to sample clock jitter. LO: Fast-settling mode (≈200 ms). Some narrow-band noise

modulation may result from jitter on the LR clocks. This signal may be asynchronous with

respect to the crystal frequency, and dynamically changed, but is normally pulled up or

pulled down on a static basis.

PWRDWN 27 36

I Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal

operation.

NC

9, 20 1, 5, 8, 11,

12, 15, 17,

19, 22, 23,

26, 29, 33,

34, 37, 39,

41, 44

No connect. Reserved. Do not connect.

Power Supply Connections

Pin Name DIP

LQFP

I/O

VDD

GND

7, 22

8, 14, 21

6, 28

I

7, 16, 27 I

Description

Positive digital voltage supply.

Digital ground. Pin 14 (DIP) and Pin 16 (LQFP) need not be decoupled.

–6–

REV. A

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