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DS2482S-800(2009) View Datasheet(PDF) - Maxim Integrated

Part Name
Description
Manufacturer
DS2482S-800
(Rev.:2009)
MaximIC
Maxim Integrated MaximIC
DS2482S-800 Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DS2482-800: Eight-Channel 1-Wire Master
Set Read Pointer
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
E1h
Pointer Code
Sets the read pointer to the specified register. Overwrites the read pointer
position of any 1-Wire communication command in progress.
To prepare reading the result from a 1-Wire Byte command; random read
access of registers.
None (can be executed at any time)
If the pointer code is not valid, the pointer code will not be acknowledged
and the command will be ignored.
None; the read pointer is updated on the rising SCL edge of the pointer
code acknowledge bit.
Not Affected
As Specified by the Pointer Code
None
None
Valid Pointer Codes
Register Selection
Status Register
Read Data Register
Channel Selection Register
Configuration Register
Code
F0h
E1h
D2h
C3h
Write Configuration
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
D2h
Configuration Byte
Writes a new configuration byte. The new settings take effect immediately.
NOTE: When writing to the Configuration Register, the new data is
accepted only if the upper nibble (bits 7 to 4) is the one's complement of
the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and parameter will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
None; the configuration register is updated on the rising SCL edge of the
configuration byte acknowledge bit.
None
Configuration Register (to verify write)
RST set to 0
1WS, SPU, APU updated
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