MCP795W20T-I/ST View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

MCP795W20T-I/ST

2Kb EE 64B SRAM WD TED ID

Microchip Technology 

MCP795W1X/MCP795W2X

2.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 2-1.

FIGURE 2-1:

DEVICE PINOUTS

SOIC/TSSOP

X1 1

X2 2

VBAT 3

WDO 4

IRQ 5

CS 6

VSS 7

14 Vcc

13 CLKOUT

12 EVHS

11 EVLS

10 SCK

9 SI

8 SO

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go in Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes into the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the

MCP795WXX. During a read cycle, data is shifted out

on this pin after the falling edge of the serial clock.

2.3 Watchdog Output (WDO)

This pin is a hardware open drain from the internal

watchdog circuit. This pin requires an external pull-up

to VCC. When a watchdog overflow occurs the on-

board N-Channel will pulse this pin low. The pulse

duration is user selectable (Address 0x0A:4). This pin

has a maximum sink current of 10mA.

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the MCP795WXX. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

2.6 Interrupt Output (IRQ)

The IRQ pin is shared with the on-board event detect

and the alarms. This pin requires an external pull-up to

VCC or VBAT. The on-board N-Channel will pull the pin

low during an event detection or an alarm. The pin

remains low until such time that the interrupt flag in the

register is cleared by software. This pin has a

maximum sink current of 10mA.

2.7 X1, X2

The X1 and X2 pins connect to the on-board oscillator

block. X1 is the input to the module and X2 is the out-

put of the module. The device can be run from an

external CMOS signal by feeding into the X1 pin. If

driving X1 the X2 pin should be a No Connect.

2.8 VBAT

The VBAT pin is a secondary supply input to maintain

the Clock and SRAM contents when VCC is removed.

2.9 CLKOUT

The CLKOUT is a push-pull output that can be used to

generate a squarewave. Please refer to Section 9.1.2,

Clockout Function for more details.

2.10 EVHS and EVLS

The EVHS and EVLS are inputs for the High and Low

Speed Event Detection circuit.

TABLE 2-1: PIN DESCRIPTIONS

Pin Name

VSS

X1

X2

VBAT

VCC

SI

WDO

SCK

CLKOUT

CS

IRQ

EVHS

EVLS

SO

Pin Function

Ground

Xtal Input, External Oscillator Input

Xtal Output

Battery Backup Input (3V Typ)

+1.8V to +3.6V Power Supply

Serial Input

Watchdog Output

Serial Clock

Clock Out

Chip Select

Interrupt Output

High-Speed Event Detect Input

Low-Speed Event Detect Input

Serial Output

DS22280C-page 6

Preliminary

 2011-2012 Microchip Technology Inc.

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