ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D41A-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

Table 60-2.

Doc. Rev.

B

SAMA5D4_11238B Datasheet Revision History (Continued)

Date Changes

Section 34. “USB High Speed Device Port (UDPHS)” (cont’d)

Section 34.7.20 “UDPHS Endpoint Status Register (Isochronous Endpoint)”: updated description of

BUSY_BANK_STA field; added “(cleared upon USB reset)” to field descriptions

Section 35. “USB Host High Speed Port (UHPHS)”

Section 35.5.3 “Interrupt Sources”: replaced instance of “Advanced Interrupt Controller (AIC)” and “AIC”

with “interrupt controller”

Section 36. “Ethernet MAC (GMAC)”

Section 36.2 “Embedded Characteristics”: updated bullet “Interrupt generation ...”

Added Section 36.5 “Product Dependencies”

Updated Section 36.6.2 “1588 Time Stamp Unit”

Reworded Section 36.6.3 “AHB Direct Memory Access Interface”

Section 36.6.3.2 “Transmit AHB Buffers”: updated third and eleventh paragraphs

Section 36.6.4 “MAC Transmit Block”: updated second paragraph

Section 36.6.5 “MAC Receive Block”: updated fourth and sixth paragraphs

Section 36.6.7 “MAC Filtering Block”: updated first and sixth paragraphs

Section 36.6.14 “IEEE 1588 Support”: added paragraph beginning “IEEE 802.1AS is mostly a subset of

1588...”

Updated Section 36.6.15 “Time Stamp Unit”

Table 36-17 “Register Mapping”:

24-Aug-15

- updated descriptions of GMAC_HRB, GMAC_HRT, GMAC_SAB1, GMAC_SAT1, GMAC_SAB2,

GMAC_SAT2, GMAC_SAB3, GMAC_SAT3, GMAC_SAB4, GMAC_SAT4, GMAC_SAMB1, and

GMAC_SAMT1, GMAC_ORLO, GMAC_ORHI, and GMAC_TSL

- new registers GMAC_RJFML (offset 0x048); GMAC_NSC (offset 0x0DC); GMAC_SCL (offset 0x0E0);

GMAC_SCH (offset 0x0E4); GMAC_EFTSH (offset 0x0E8); GMAC_EFRSH (offset 0x0EC);

GMAC_PEFTSH (offset 0x0F0); GMAC_PEFRSH (offset 0x0F4); GMAC_TISUBN (offset 0x1BC);

GMAC_TSH (offset 0x1C0)

- removed GMAC_TSSSL (offset 0x1C8) and GMAC_TSSN (offset 0x1CC)

- offset 0x1E0: PTP Event Frame Transmitted Seconds / GMAC_EFTS replaced by PTP Event Frame

Transmitted Seconds Low Register / GMAC_EFTSL

- offset 0x1E8: PTP Event Frame Received Seconds / GMAC_EFRS replaced by PTP Event Frame

Received Seconds Low Register / GMAC_EFRSL

- offset 0x1F0: PTP Peer Event Frame Transmitted Seconds / GMAC_PEFTS replaced by PTP Peer Event

Frame Transmitted Seconds Low Register / GMAC_PEFTSL

- offset 0x1F8: PTP Peer Event Frame Received Seconds / GMAC_PEFRS replaced by PTP Peer Event

Frame Received Seconds Low Register / GMAC_PEFRSL

- updated reserved space

Section 36.8.6 “GMAC Transmit Status Register”: updated TXGO bit description

Section 36.8.9 “GMAC Receive Status Register”: updated RXOVR bit description

Section 36.8.11 “GMAC Interrupt Enable Register”: updated bit descriptions

Section 36.8.12 “GMAC Interrupt Disable Register”: updated bit descriptions

Section 36.8.13 “GMAC Interrupt Mask Register”: updated bit descriptions

Section 36.8.14 “GMAC PHY Maintenance Register”: added content on Clause 22/Clause 45 PHYs

read/write access; updated CLTTO bit description

Added Section 36.8.17 “GMAC RX Jumbo Frame Max Length Register”

Added Section 36.8.38 “GMAC 1588 Timer Nanosecond Comparison Register”

Added Section 36.8.39 “GMAC 1588 Timer Second Comparison Low Register”

SAMA5D4 Series [DATASHEET]

Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16

1791

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