DSPIC33FJ128MC202 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ128MC202

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

Revision C (May 2009)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

Global changes include:

• Changed all instances of OSCI to OSC1 and

OSCO to OSC2

• Changed all instances of VDDCORE and VDDCORE/

VCAP to VCAP/VDDCORE

The other changes are referenced by their respective

section in the following table.

TABLE A-2: MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit Digital

Signal Controllers”

Updated all pin diagrams to denote the pin voltage tolerance (see “Pin

Diagrams”).

Section 1.0 “Device Overview”

Section 2.0 “Guidelines for Getting

Started with 16-bit Digital Signal

Controllers”

Section 3.0 “CPU”

Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which

references pin connections to VSS.

Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).

Added new section to the data sheet that provides guidelines on getting

started with 16-bit Digital Signal Controllers.

Updated CPU Core Block Diagram with a connection from the DSP Engine

to the Y Data Bus (see Figure 3-1).

Section 4.0 “Memory Organization”

Vertically extended the X and Y Data Bus lines in the DSP Engine Block

Diagram (see Figure 3-3).

Updated Reset value for CORCON in the CPU Core Register Map (see

Table 4-1).

Removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register Map

(see Table 4-4).

Updated bit locations for RPINR25 in the Peripheral Pin Select Input

Register Map (see Table 4-24).

Section 5.0 “Flash Program

Memory”

Section 9.0 “Oscillator

Configuration”

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 4-36).

Updated Section 5.3 “Programming Operations” with programming time

formula.

Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).

Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock

Divisor (CLKDIV) Register (see Register 9-2).

Added a paragraph regarding FRC accuracy at the end of Section 9.1.1

“System Clock Sources”.

Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.

Section 10.0 “Power-Saving

Features”

Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see

Register 9-4).

Added the following registers:

• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)

• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)

• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)

© 2007-2012 Microchip Technology Inc.

DS70291G-page 441

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