74LVC373AD View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
74LVC373AD
NXP Semiconductors.
74LVC373AD Datasheet PDF : 19 Pages
| |||
NXP Semiconductors
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3. Functional table[1]
Operating modes
Input
OE
LE
Dn
Enable and read register L
(transparent mode)
L
H
L
H
H
Latch and read register
L
L
l
L
L
h
Latch register and disable H
L
l
outputs
H
L
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High-impedance OFF-state
7. Limiting values
Internal latch
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC
supply voltage
IIK
input clamping current
VI < 0
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0
VO
output voltage
HIGH or LOW-state
3-state
0.5
50
[1] 0.5
-
[2] 0.5
[2] 0.5
+6.5
V
-
mA
+6.5
V
50
mA
VCC + 0.5 V
+6.5
V
IO
ICC
IGND
Tstg
Ptot
output current
supply current
ground current
storage temperature
total power dissipation
VO = 0 V to VCC
Tamb = 40 C to +125 C
-
50
mA
-
100
mA
100 -
mA
65 +150
C
[3] -
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 22 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 19
Share Link: