C8051F996-C-GMR View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

C8051F996-C-GMR

Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

Unspecified 

C8051F99x-C8051F98x

Figure 5.10. Voltage Reference Functional Block Diagram...................................... 88

Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 93

Figure 7.2. Comparator Hysteresis Plot ................................................................... 95

Figure 7.3. CP0 Multiplexer Block Diagram.............................................................. 98

Figure 8.1. CS0 Block Diagram .............................................................................. 100

Figure 8.2. Auto-Scan Example.............................................................................. 103

Figure 8.3. CS0 Multiplexer Block Diagram............................................................ 117

Figure 9.1. CIP-51 Block Diagram.......................................................................... 119

Figure 10.1. C8051F99x-C8051F98x Memory Map ............................................... 128

Figure 10.2. Flash Program Memory Map.............................................................. 129

Figure 14.1. Flash Program Memory Map (8 kB and smaller devices) .................. 152

Figure 15.1. C8051F99x-C8051F98x Power Distribution....................................... 163

Figure 16.1. CRC0 Block Diagram ......................................................................... 172

Figure 16.2. Bit Reverse Register .......................................................................... 179

Figure 18.1. Reset Sources.................................................................................... 181

Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 182

Figure 19.1. Clocking Sources Block Diagram ....................................................... 188

Figure 19.2. 25 MHz External Crystal Example...................................................... 190

Figure 20.1. SmaRTClock Block Diagram.............................................................. 197

Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 206

Figure 21.1. Port I/O Functional Block Diagram ..................................................... 215

Figure 21.2. Port I/O Cell Block Diagram ............................................................... 216

Figure 21.3. Peripheral Availability on Port I/O Pins............................................... 219

Figure 21.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped).

220

Figure 21.5. Crossbar Priority Decoder in Example Configuration (4 Pins Skipped) ...

220

Figure 22.1. SMBus Block Diagram ....................................................................... 235

Figure 22.2. Typical SMBus Configuration ............................................................. 236

Figure 22.3. SMBus Transaction ............................................................................ 237

Figure 22.4. Typical SMBus SCL Generation......................................................... 240

Figure 22.5. Typical Master Write Sequence ......................................................... 249

Figure 22.6. Typical Master Read Sequence ......................................................... 250

Figure 22.7. Typical Slave Write Sequence ........................................................... 251

Figure 22.8. Typical Slave Read Sequence ........................................................... 252

Figure 23.1. UART0 Block Diagram ....................................................................... 257

Figure 23.2. UART0 Baud Rate Logic .................................................................... 258

Figure 23.3. UART Interconnect Diagram .............................................................. 259

Figure 23.4. 8-Bit UART Timing Diagram............................................................... 259

Figure 23.5. 9-Bit UART Timing Diagram............................................................... 260

Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 261

Figure 24.1. SPI Block Diagram ............................................................................. 265

Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 267

Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram

267

Rev. 1.3

9

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