CP2114-PCM1774EK View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

CP2114-PCM1774EK

CP2114 EVALUATION KIT USER’S GUIDE

Unspecified 

CP2114-EK

5.1.3. UART Signals (J3)

An RS-232 transceiver circuit and DB9 connector (J3) are provided on the evaluation board to connect the CP2114

to external serial devices. See Table 3 for the RS-232 J3 pin descriptions.

Table 3. RS-232 Pin Descriptions

Pin

Signal

CP2114

Direction

2

RXD

Input

3

TXD

Output

5

GND

7

RTS

Output

8

CTS

Input

Description

Receive Data

Transmit Data

Ground

Request to Send

Clear to Send

5.1.4. CP2114 Pin Connectors (JP00-JP30)

The JP00-JP30 connectors connect and disconnect CP2114 pins from external circuits. By default, all of these

jumpers are populated.

5.1.5. VIO Power Connector (JP40)

This header (JP40) is included on the evaluation board to provide VIO power options. Populating the shorting block

connects the CP2114 VIO input (pin 6) to CP2114 VDD (pin 7). Remove the shorting block to power VIO from an

external source and connect the power source to pin 2 of the header.

5.1.6. REGIN Power Connector and Self-Powered Mode Connector (JP41)

The JP41 header is used to connect the CP2114 REGIN pin (pin 8) to the VBUS source from the USB connector

(default) or to the CP2114 VDD pin (pin 7). When connected to the VBUS source, the device is intended for bus-

powered operation. When connected to the CP2114 VDD pin, the device is intended for self-powered operation. In

self-powered operation, an external power source can be connected to the JP41 header to power the VDD pin

directly.

5.1.7. Test Point Connector (JP42)

The JP42 header contains test points and is not used in normal operation.

5.1.8. Si500 Enable Connector (JP43)

The JP43 header controls the power to the Si500 CMOS clock. Shorting pin 1 to pin 2 on the header will connect

CP2114 VDD (pin 7) to the Si500. Shorting pin 2 to pin 3 on the header will place the Si500 in powerdown mode.

The setting of JP43 depends on the desired clocking mode.

5.1.9. SCK to SCKIN Connector (JP44)

The JP44 jumper should be left installed.

5.1.10. DAC Selection Connector (JP45)

The JP45 header is used to select the CP2114 boot configuration after a reset. When a jumper is populated, the

corresponding GPIO pin in connected to ground. When a jumper is removed, the corresponding GPIO pin is

weakly pulled high.

Note: If any of the four DAC select pins are configured for a function other than DAC selection, the CP2114 will not use the

DAC select pins to choose a boot configuration.

5.1.11. Green USB ACTIVE LED and Connector (JP46, D6)

The JP46 header is used to connect the CP2114 SUSPEND pin (pin 18) to the D6 green LED. When the LED is on,

the device has enumerated with the PC operating normally. When the LED is off, the device has not yet

enumerated or is in the USB Suspend state.

5.1.12. .Red USB SUSPEND LED and Connector (JP47, D5)

10

Rev. 0.1

Share Link: