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S24CSO View Datasheet(PDF) - Seiko Instruments Inc

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S24CSO Datasheet PDF : 37 Pages
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FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM
S-24CS01A/02A/04A H Series
Rev.3.1_03
8. Address increment timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the read data in
read operation and the falling edge of the SCL clock for the 8th bit of the received data in write operation.
SCL
8
9
1
8
9
SDA
R / W=1
ACK Output
D7 Output
D0 Output
SCL
SDA
Address Increment
Figure 18 Address Increment Timing in Reading
8
9
1
R / W=0
ACK Output D7 Input
8
9
D0 Input
ACK Output
Address Increment
Figure 19 Address Increment Timing in Writing
Write Protect Function during the Low Power Supply Voltage
The S-24CS01A/02A/04A has a detection circuit for low power voltage. The detection circuit cancels a write instruction
when the power voltage is low or the power switch is on. The detection voltage is 1.75 V typically and the release
voltage is 2.05 V typically, the hysteresis of approximate 0.3 V thus exists. (See Figure 20.)
When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.
When the power voltage lowers during a data transmission or a write operation, the data at the address of the operation
is not assured.
Power supply voltage
Hysteresis width
0.3 V approximately
Detection voltage (-VDET)
1.75 V typ.
Release voltage (+VDET)
2.05 V typ.
Write Instruction
cancel
Figure 20 Operation during Low Power Supply Voltage
18

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