HMT325S6CFR8C-PB View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

Manufacturer

HMT325S6CFR8C-PB

204pin DDR3 SDRAM SODIMM

Hynix Semiconductor 

Cross point voltage for differential input signals (CK, DQS)

Symbol

Parameter

DDR3-800, 1066, 1333, 1600

Min

Max

Unit Notes

VIX(CK)

VIX(DQS)

Differential Input Cross Point Voltage

relative to VDD/2 for CK, CK

Differential Input Cross Point Voltage

relative to VDD/2 for DQS, DQS

-150

-175

-150

150

mV 2

175

mV 1

150

mV 2

Notes:

1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are

monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential

slew rate of CK - CK is larger than 3 V/ns.

Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 19

for VSEL and VSEH standard values.

2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.

(VDD/2) + Vix (Min) - VSEL ≥ 25mV

VSEH - ((VDD/2) + Vix(Max)) ≥ 25mV

Slew Rate Definitions for Single-Ended Input Signals

See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3 Device Operation” for single-ended slew

rate definitions for address and command signals.



See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3 Device Operation” for single-ended slew rate

definition for data signals.

Rev. 1.0/Sep. 2012

20

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