®
Rev. 1.3
LY6225616
256K X 16 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL
TEST CONDITION
VCC for Data Retention VDR CE# ≧ VCC - 0.2V
LL
Data Retention Current
VCC = 1.5V
IDR CE# ≧ VCC - 0.2V
25℃
SL
Other pins at 0.2V or VCC-0.2V
40℃
SL
Chip Disable to Data
Retention Time
tCDR
See Data Retention
Waveforms (below)
Recovery Time
tR
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
MIN.
1.5
-
-
-
-
0
tRC*
TYP.
-
2
2
MAX.
5.5
30
8
UNIT
V
µA
µA
2
8
µA
2
23 µA
-
-
ns
-
-
ns
Vcc
CE#
Vcc(min.)
tCDR
VIH
VDR ≧ 1.5V
CE# ≧ Vcc-0.2V
Vcc(min.)
tR
VIH
Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)
Vcc
LB#,UB#
Vcc(min.)
tCDR
VIH
VDR ≧ 1.5V
LB#,UB# ≧ Vcc-0.2V
Vcc(min.)
tR
VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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