MPC8270VR View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8270VR

PowerQUICC II Family Hardware Specifications

Freescale Semiconductor 

Thermal Characteristics

4.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple

two-resistor model can be used with the thermal simulation of the application, or a more accurate and

complex model of the package can be used in the thermal simulation.

4.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a

measurement of the temperature at the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD)

where:

ΨJT = thermal characterization parameter

TT = thermocouple temperature on top of package

PD = power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge

type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned

so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is

placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple

wire.

4.6 Layout Practices

Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies.

Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins

drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground

using bypass capacitors located as close as possible to the four sides of the package. For filtering high

frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium

frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also

recommended. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH

and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner

layers for power and GND planes.

All output pins on the SoC have fast rise and fall times. Printed circuit (PC) trace interconnection length

should be minimized to minimize overdamped conditions and reflections caused by these fast output

switching times. This recommendation particularly applies to the address and data buses. Maximum PC

trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as

well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient

currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

14

Freescale Semiconductor

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