CY7C1360V25-166AC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360V25-166AC Datasheet PDF : 31 Pages
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PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Locations x36 Pin Locations Name
85
85
ADSC
31
31
MODE
64
64
ZZ
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8, 9, 12, 13, 18,
19, 22, 23
(a) 52, 53, 56–59,
62, 63
(b) 68, 69, 72–75,
78, 79
(c) 2, 3, 6–9, 12, 13
(d) 18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
74, 24
51, 80, 1, 30
NC,DQPa
NC,DQPb
NC,DQPc
NC,DQPd
15, 41, 65, 91
15, 41, 65, 91
VDD
17, 40, 67, 90
17, 40, 67, 90
VSS
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 21, 26, 55,
60, 71, 76
1, 2, 3, 6, 7, 14, 16,
25, 28, 29, 30, 51,
52, 53, 56, 57, 66,
75, 78, 79, 95, 96
42
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
16, 66
42
VDDQ
VSSQ
NC
DNU
38, 39
38, 39
DNU
I/O
Input-
Synchronous
Input-
Static
Input-
Asynchronous
I/O-
Synchronous
I/O-
Synchronous
Power Supply
Ground
I/O Power
Supply
I/O Ground
-
Description
Address Strobe from Controller, sampled on the ris-
ing edge of CLK. When asserted LOW, A[x:0] is cap-
tured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Selects Burst Order. When tied to GND selects lin-
ear burst sequence. When tied to VDDQ or left float-
ing selects interleaved burst sequence. This is a
strap pin and should remain static during device
operation.
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with
data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQa and DPa are placed in a
three-state condition.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQx and DPx are placed in a
three-state condition.
These are not connect pins on the CY7C1364.
Power supply inputs to the core of the device.
Should be connected to 2.5V power supply.
Ground for the core of the device. Should be con-
nected to ground of the system.
Power supply for the I/O circuitry. Should be con-
nected to a 2.5V power supply.
Ground for the I/O circuitry. Should be connected
to ground of the system.
No Connects.
Do Not Use Pin. This pin is used for the expansion
to the 16M density.
Do Not Use Pins. These pins should be left floating
or tied to VSS.
5
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