CY7C1360V25-166BGC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360V25-166BGC Datasheet PDF : 31 Pages
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PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Definitions (119-Ball BGA) (continued)
x18 Pin Locations x36 Pin Locations Name
3R
3R
MODE
7T
7T
ZZ
(a) 6F, 6H, 6L, 6N, (a) 6K, 6L, 6M, 6N, DQa
7E, 7G, 7K, 7P
7K, 7L, 7N, 7P
DQb
(b) 1D, 1H, 1L, 1N, (b) 6E, 6F, 6G, 6H, DQc
2E, 2G, 2K, 2M 7D, 7E, 7G, 7H
DQd
(c) 1D, 1E, 1G, 1H,
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
2K, 2L, 2M, 2N
U5
U5
TDO
U3
U3
TDI
U2
U2
TMS
U4
6D, 2P
U4
6P, 6D, 2D, 2P
TCK
NC,DQPa
NC,DQPb
NC,DQPc
NC,DQPd
2J, 4C, 4J, 4R, 5R, 2J, 4C, 4J, 4R, 5R, 6J VDD
6J
3D, 3E, 3F, 3H, 3K, 3D, 3E, 3F, 3H, 3K, VSS
3M, 3N, 3P, 5D, 5E, 3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N, 5F, 5H, 5K, 5M, 5N,
5P
5P
I/O
Input-
Static
Input-
Asynchronous
I/O-
Synchronous
JTAG Serial
Output
Synchronous
JTAG Serial
Input
Synchronous
Test Mode
Select
Synchronous
JTAG-Clock
I/O-
Synchronous
Power Supply
Ground
Description
Selects Burst Order. When tied to GND selects lin-
ear burst sequence. When tied to VDDQ or left float-
ing selects interleaved burst sequence. This is a
strap pin and should remain static during device
operation.
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with
data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the ris-
ing edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When
HIGH, DQx and DQPx are placed in a three-state
condition.
Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK.
This pin controls the Test Access Port state ma-
chine. Sampled on the rising edge of TCK.
Clock input to the JTAG circuitry.
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the ris-
ing edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When
HIGH, DQx and DPx are placed in a three-state con-
dition.
These are not connect pins on the CY7C1364
Power supply inputs to the core of the device.
Should be connected to 2.5V power supply.
Ground for the device. Should be connected to
ground of the system.
1A, 1F, 1J, 1M, 1U, 1A, 1F, 1J, 1M, 1U, VDDQ
7A, 7F, 7J, 7M, 7U 7A, 7F, 7J, 7M, 7U
1B, 1C, 1E, 1G, 1K, 1B, 1C, 1R, 1T, 2T, NC
1P, 1R, 1T, 2D, 2F, 3J, 4D, 4L, 5J, 6T, 7B,
2H, 2L, 2N, 3J, 4D, 7C, 7R
4L, 4T, 5J, 6E, 6G,
6K, 6M, 6P, 7B, 7C,
7D, 7H, 7L, 7N, 7R
6U
6U
DNU
I/O Power
Supply
-
Power supply for the I/O circuitry. Should be con-
nected to a 2.5V power supply.
No Connects.
Do Not Use Pins. These pins should be left floating.
7
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