CY7C1360V25-166AC View Datasheet(PDF) - Cypress Semiconductor
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CY7C1360V25-166AC Datasheet PDF : 31 Pages
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PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.1 ns (200-MHz
device).
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports
secondary cache in systems utilizing either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486 processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the Pro-
cessor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst se-
quence is controlled by the ADV input. A two-bit on-chip wrap-
around burst counter captures the first address in a burst se-
quence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1360V25/
CY7C1364V25 and BWa,b for CY7C1362V25) inputs. A Global
Write Enable (GW) overrides all byte write inputs and writes
data to all four bytes. All writes are simplified with on-chip syn-
chronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.1 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state; its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
is loaded into the address register and the address advance-
ment logic while being delivered to the RAM core. The write
signals (GW, BWE, and BWx) and ADV inputs are ignored dur-
ing this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx sig-
nals. The CY7C1360V25/1364V25/1362V25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write ( BWa,b,c,d for CY7C1360V25/1364V25 &
BWa,b for CY7C1362V25) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Because the CY7C1360V25/CY7C1364V25/CY7C1362V25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQ inputs. Do-
ing so will three-state the output drivers. As a safety precau-
tion, DQ are automatically three-stated whenever a write cycle
is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWx) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a sin-
gle clock cycle to complete. The address presented to A[17:0]
is loaded into the address register and the address advance-
ment logic while being delivered to the RAM core. The ADV
input is ignored during this cycle. If a global write is conducted,
the data presented to the DQ[x:0] is written into the correspond-
ing address location in the RAM core. If a byte write is conduct-
ed, only the selected bytes are written. Bytes not selected dur-
ing a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1360V25/CY7C1364V25/CY7C1362V25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQ[x:0] inputs.
Doing so will three-state the output drivers. As a safety precau-
tion, DQ[x:0] are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1360V25/CY7C1364V25/CY7C1362V25 provides
a two-bit wraparound counter, fed by A[1:0], that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pen-
tium applications. The linear burst sequence is designed to
support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
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