CY7C1360V25-133BGC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1360V25-133BGC Datasheet PDF : 31 Pages
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PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
A[1:0]]
00
01
10
11
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode
standby current
ZZ > VDD − 0.2V
tZZS
Device operation to ZZ > VDD − 0.2V
ZZ
tZZREC
ZZ recovery time
ZZ < 0.2V
Linear Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
10
11
00
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
Min
2tCYC
Max
15
2tCYC
Unit
mA
ns
ns
9
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