T2080 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

T2080

T2080 Product Brief Also supports T2081

Freescale Semiconductor 

Chip features

Power Architecture Power Architecture Power Architecture Power Architecture

e6500

e6500

e6500

e6500

32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB

D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache

2 MB Banked L2

512 KB

Plat Cache

64-bit DDR3/3L

with ECC

MPIC

PreBoot Loader

Security Monitor

Internal BootROM

Power mgmt

SDXC/eMMC

eSPI

2 x DUART

4x I2C

IFC

2 x USB2.0 w/PHY

Clocks/Reset

GPIO

CCSR

PAMU

CoreNet TM

Coherency Fabric

PAMU

PAMU (peripheral access management unit)

SEC QMan

PME

DCE

BMan

RMan

FMan

Parse, classify,

distribute

Buffer

HiGig

DCB

1GE 1GE

4x 1/2.5/10G

1GE 1GE

8 lanes up to 10 GHz SerDes

DMAx3

Real-time

debug

Watch point

cross-

trigger

Perf CoreNet

Monitor trace

Aurora

8 lanes up to 8 GHz SerDes

Figure 3. T2080 block diagram

4.2 Features summary

This chip includes the following functions and features:

• 4, dual-threaded e6500 cores built on Power Architecture® technology sharing a 2 MB L2 cache

• Up to 1.8 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)

• 512 KB CoreNet platform cache (CPC)

• Hierarchical interconnect fabric

• CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation

amongst CoreNet end-points

• Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling

• One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support

• Memory pre-fetch engine

• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:

• Packet parsing, classification, and distribution (Frame Manager)

• Queue management for scheduling, packet sequencing, and congestion management (Queue Manager)

• Hardware buffer management for buffer allocation and de-allocation (BMan)

• Cryptography acceleration (SEC 5.2) at up to 10 Gbps

• RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps

• Decompression/Compression Acceleration (DCE) at up to 17.5 Gbps

• DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN)

• 16 SerDes lanes at up to 10.3125 GHz

• Eight Ethernet interfaces, supporting combinations of the following:

T2080 Product Brief, Rev 0, 04/2014

4

Freescale Semiconductor, Inc.

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