T2080 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

T2080

T2080 Product Brief Also supports T2081

Freescale Semiconductor 

• Bulk

• Control

• Interrupt

• Isochronous

Chip features

4.9 High-speed peripheral interface complex (HSSI)

The SoC offers a variety of high-speed serial interfaces, sharing a set of 16 SerDes lanes. Each interface is backed by a high

speed serial interface controller. The SoC has the following types and quantities of controllers:

• Four PCI Express controllers, one Gen 3.0 PCI Express controller with SRIOV, one Gen 3.0 PCI Express controller

without SRIOV and two PCI Express Gen 3.0 controllers

• Two Serial RapidIO 2.0

• Two SATA 2.0

• Up to eight Ethernet controllers with various protocols

• Aurora

The features of each high-speed serial controller are described in the subsequent sections. Debug functionality is described in

Debug support."

4.9.1 PCI Express

This chip instantiates four PCI Express controllers, each with the following key features:

• One PCI Express controller supports end-point SR-IOV.

• Two physical functions

• 64 virtual functions per physical function

• Eight MSI-X per either physical function or virtual function

• Two PCI Express controllers support 2.0 (maximum lane width off x8).

• Two PCI Express controllers support 3.0 (maximum lane width of x4).

• Power-on reset configuration options allow root complex or endpoint functionality.

• x8, x4, x2, and x1 link widths support

• Both 32- and 64-bit addressing and 256-byte maximum payload size

• Inbound INTx transactions

• Message signaled interrupt (MSI) transactions

4.9.2 Serial RapidIO

The Serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 2.1 . RapidIO is a high-

performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be used in a variety of

applications as an open standard. The rich feature set includes high data bandwidth, low-latency capability, and support for

high-performance I/O devices as well as message-passing and software-managed programming models. Receive and transmit

ports operate independently, and with 2 x 4 Serial RapidIO controllers, the aggregate theoretical bandwidth is 32 Gbps.

The chip offers two Serial RapidIO controllers Receive and transmit ports operate independently and with 2 x 4 Serial

RapidIO controllers; the aggregate theoretical bandwidth is 32 Gbps. The Serial RapidIO controllers can be used in

conjunction with "Rapid IO Message Manager (RMAN), as described in RapidIO Message Manager (RMan 1.0)."

Key features of the Serial RapidIO interface unit include the following:

• Support for RapidIO Interconnect Specification, Revision 2.1 (All transaction flows and priorities.)

T2080 Product Brief, Rev 0, 04/2014

Freescale Semiconductor, Inc.

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