STK672-060 View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

STK672-060

Unipolar constant-current chopper (external excitation PWM) circuit with built- in microstepping controller

SANYO -> Panasonic 

STK672-060

• Input Signal Functions and Timing

CLK (Phase switching clock)

Input frequency range: DC to 50 kHz

Minimum pulse width: 10 µs

Duty: 40 to 60% (The minimum pulse width takes precedence when M3 is high)

Pin circuit type: CMOS Schmitt trigger with built-in pull-up resistor (20 kΩ typical)

A multi-stage noise filter is built in.

Function

When M3 is high or open: The excited phase is advanced by one step on each rising edge of CLK signal.

When M3 is low: The phase is advanced 2 steps on the rising and falling edges of the CLK signal.

CLK Input Acquisition Timing (when M3 is low)

CLK input

System clock

Phase excitation counter clock

Control output timing

Excitation counter up/down

Control output switching timing

A13264

CWB (Rotation setting procedure)

Pin circuit type: CMOS Schmitt trigger with built-in pull-up resistor (20 kΩ typical)

Function

When CWB is low: Rotation in the clockwise direction.

When CWB is high: Rotation in the counterclockwise direction

Note: When M3 is low, the CWB input must not be changed within ±6.25 µs of a rising or falling edge on the CLK

input.

RETURN (Forcible return to the origin point for the current phase)

Pin circuit type: CMOS Schmitt trigger with built-in pull-up resistor (20 kΩ typical)

Built-in noise filter

Note: The motor is forcibly moved to the origin point for the current phase by changing the input level on this pin from

low to high. When unused, this pin must normallyr be left open or connected to the VCC2.

ENABLE (On/off control of the A, A, B, and B excitation drive outputs and selection of the internal operate or hold

state of the hybrid IC itself)

Pin circuit type: CMOS Schmitt trigger with built-in pull-up resistor (20 kΩ typical)

Function

When ENABLE is high or open: Normal operating state

When ENABLE is low: The hybrid IC goes to the hold state, and the excitation drive output (motor current) is

forcibly turned off (the output current is cut off). In this state, the hybrid IC system clock is

stopped, and the hybrid IC is not affected by any changes in the state of the input pins other

than the reset input.

No. 7441-9/19

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