MAC7101CAG50 View Datasheet(PDF) - Freescale Semiconductor
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MAC7101CAG50 Datasheet PDF : 56 Pages
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Electrical Characteristics
3.8.3 PLL Characteristics
Table 20. PLL Characteristics
Num C
Rating
Symbol Min
Typ
Max Unit
K1
PLL reference frequency, crystal oscillator range
fREF
0.5
—
16 MHz
K2 P Self Clock Mode frequency
K3 D VCO locking range
fSCM
2
fVCO 1
8
K4 D Lock Detector transition from Acquisition to Tracking mode |Δtrk|
3
K5 D Lock Detection
|ΔLock|
0
K6 D Un-Lock Detection
|Δunl|
0.5
K7 D Lock Detector transition from Tracking to Acquisition mode |Δunt|
6
K8 C PLLON Total Stabilization delay (Auto Mode) 3
tstab
—
K9 D PLLON Acquisition mode stabilization delay 3
tacq
—
K10 D PLLON Tracking mode stabilization delay 3
tal
—
—
—
—
—
—
—
0.5 4
0.3 4
0.2 4
5.5 MHz
50 MHz
4
%2
1.5
%2
2.5
%2
8
%2
35
ms
15
ms
25
ms
K11 D Charge pump current acquisition mode
| ich |
—
38.5
—
μA
K12 D Charge pump current tracking mode
| ich |
—
3.5
—
μA
K13 D Jitter fit VCO loop gain parameter
K1
—
–195
— MHz/V
K14 D Jitter fit VCO loop frequency parameter
K15 C Jitter fit parameter 1
K16 C Jitter fit parameter 2
f1
—
126
— MHz
j1
—
—
1.3
%4
j2
—
—
0.12 % 4
NOTES:
1. If CLKSEL[PLLSEL] is set then the system clock (fSYS) is equal to fVCO, otherwise it is equal to fOSC (table Table 19,
J1a or J1b). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.
2. Percentage deviation from target frequency
3. PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
4. fOSC = 4 MHz, fVCO = 40 MHz (REFDV = 0x00, SYNR = 0x04), CS = 2.2 nF, CP = 220 pF, RS = 5.6 KΩ.
5. fOSC = 4 MHz, fVCO = 16 MHz (REFDV = 0x00, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS = 2.7 KΩ.
3.8.4 Crystal Monitor Time-out
The time-out Table 21 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
Table 21. Crystal Monitor Time-Outs
Min
Typ
Max
Unit
6
10
18.5
μs
3.8.5 Clock Quality Checker
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 20. These numbers define the upper time limit for the individual check windows to complete.
Table 22. CRG Maximum Clock Quality Check Timings
Clock Check Windows
Value
Unit
Check Window
9.1 to 20.0
ms
Timeout Window
0.46 to 1.0
s
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
18
Preliminary
Freescale Semiconductor
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