MAC7101VPV50 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MAC7101VPV50

Microcontroller Family Hardware Specifications

Freescale Semiconductor 

Electrical Characteristics

3.9 External Bus Timing

Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay

with respect to the rising edge of a reference clock. The reference clock is the

CLKOUT output. All other timing relationships can be derived from these values.

Table 24. External Bus Input Timing Specifications 1

Num C

Rating

Symbol Min Max Unit

M1 P CLKOUT period 2

Control Inputs

M2a P Control input valid to CLKOUT high 3

M3a P CLKOUT high to control inputs invalid 3

Data Inputs

tCYC

20 — ns

tCVCH 13 — ns

tCHCII

0

— ns

M4 P Data input (DATA[15:0]) valid to CLKOUT high

tDIVCH

9

— ns

M5 P CLKOUT high to data input (DATA[15:0]) invalid

tCHDII

0

— ns

NOTES:

1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).

2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,

K3); if it is clear then fSYS is equal to fOSC (table Table 19, J1a or J1b). Throughout this document, tCYC is used to

specify a unit of time equal to 1 ÷ CLKOUT (which is equal to tfsys).

3. The TA pin is the only control input on MAC7100 family devices.

CLKOUT (50 MHz)

Input Setup & Hold

Input Rise Time

Input Fall Time

tSETUP

Invalid

1.5 V

1.5 V Valid 1.5 V

tHOLD

Invalid

VH = VIH

VL = VIL

VH = VIH

VL = VIL

tRISE = 1.5 ns

tFALL = 1.5 ns

CLKOUT

M4

M5

Inputs

Figure 6. General Input Timing Requirements

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

20

Preliminary

Freescale Semiconductor

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