ADF7023BCPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF7023BCPZ Datasheet PDF : 112 Pages
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Data Sheet
ADF7023
Peripheral Features..........................................................................83
Analog-to-Digital Converter .....................................................83
Temperature Sensor ....................................................................83
Test DAC ......................................................................................83
Transmit Test Modes ..................................................................83
Silicon Revision Readback .........................................................83
Applications Information ...............................................................84
Application Circuit .....................................................................84
REVISION HISTORY
7/12—Rev. B to Rev. C
Changes to Features Section ............................................................1
Changed 1.8 V to 2.2 V, General Description Section .................4
Changed 1.8 V to 2.2 V, Table 1 Summary ....................................6
Changed 1.8 V to 2.2 V, Table 2.......................................................7
Changes to Table 3 ............................................................................9
Changes to Table 5 ..........................................................................14
Changes to VDD Parameter, Table 6...............................................15
Changes to Timing Specifications Section...................................16
Deleted t1 from Table 7, Figure 2, and Figure 3...........................16
Changes to Table 9 ..........................................................................18
Changes to Figure 5 to Figure 10 ..................................................20
Changes to Figure 11, Figure 12 Caption, Figure 13 and
Figure 14 Caption............................................................................21
Changes to Figure 19 Caption to Figure 21 Caption..................22
Changes to Figure 26 Caption .......................................................23
Changes to Figure 34 Caption .......................................................24
Changes to Figure 61 Caption and Figure 64 Caption...............29
Changes to Figure 72 ......................................................................31
Changes to PHY_SLEEP Section ..................................................33
Changes to Initialization After Application of Power Section,
Initialization After Issuing the CMD_HW_RESET Command
Section, Initialization on Transitioning from PHY_SLEEP
(After CS Is Brought Low) Section, and Initialization After a
WUC Timeout Section...................................................................35
Changes to CMD_RAM_LOAD_DONE (0xC7) Section .........37
Deleted CMD_SYNC (0xA2) Section ..........................................37
Changes to State Transition and Command Timing Section....38
Changes to Table 11 and Table 12 .................................................39
Changes to Addressing Section .....................................................45
Changes to Example Address Check Section, Table 18, and CRC
Section ..............................................................................................46
Changes to Figure 79 ......................................................................47
Changes to Figure 81 and Figure 82 .............................................50
Changes to Figure 83 and Figure 84 .............................................51
Changes to CMD_FINISHED Description, Table 24.................53
Changes to Command Access Section .........................................56
Changes to Figure 97 ......................................................................63
Changes to Table 29 ........................................................................68
Added Calibrating the RC Oscillator Section, Performing a Fine
Calibration of the RC Oscillator Section, and Performing a
Coarse Calibration of the RC Oscillator Section ........................69
Host Processor Interface ............................................................85
PA/LNA Matching ......................................................................85
Command Reference ......................................................................87
Register Maps ..................................................................................88
BBRAM Register Description ...................................................90
MCR Register Description.......................................................100
Outline Dimensions......................................................................109
Ordering Guide .........................................................................109
Added Figure 103; Renumbered Sequentially.............................70
Changes to Writing a Module to Program RAM Section..........71
Changes to Automatic PA Ramp Section Equation and Image
Channel Rejection Section.............................................................75
Changes to Temperature Sensor Section and Table 43 ..............83
Changes to Figure 110 ....................................................................84
Changes to Figure 111 and Figure 112.........................................85
Changes to Support for External PA and LNA Control Section
and Table 45 .....................................................................................86
Changes to CMD_SYNC Description Column, Table 46..........87
Changes to Table 48 ........................................................................88
Changes to Table 49 ........................................................................89
Changes to SYNTH_LUT_CONTROL_1 Description Column,
Table 70.............................................................................................93
Changes to Table 78 ........................................................................96
Changes to Table 79 ........................................................................97
Changes to Table 84 and Table 86 .................................................98
Changes to Table 94 ........................................................................99
Added Table 95, Table 96, and Table 97; Renumbered
Sequentially ....................................................................................100
Changes to Table 101 ....................................................................101
Added Table 124 and Table 125...................................................105
3/11—Rev. A to Rev. B
Changes to RSSI Method 3, Formula ...........................................72
Changes to RSSI Method 4, Step 3................................................72
Changes to RSSI Method 4, Step 5 Formula and Formula
Approximation ................................................................................73
Added Register 0x361 to Table 49.................................................85
Added Table 129, Renumbered Subsequent Tables ..................104
2/11—Rev. 0 to Rev. A
Changes to Table 9, DGUARD Description ................................18
Changes to Sport Mode in Receive Section.................................47
Changes to Crystal Oscillator Section, Typical Crystal Load
Capacitance Tuning Range Value, and to Table 31.....................70
Changes to RSSI Method 3 Section ..............................................72
Changes to RSSI Method 4 Section ..............................................73
Changes to Table 41, 9.6 kbps and 1 kbps Data Rate
Setup Values .....................................................................................78
Changes to Table 108, ADC_PD_N Description......................100
8/10—Revision 0: Initial Version
Rev. C | Page 3 of 112
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