MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
P5OUT
INTFLG
INTEN
INTFLG
INTEN
45h (r/w) P57 P56
50h (r/w) HPRchg VPRchg
60h (w) EHPR EVPR
51h(r/w) X
X
61h(w) X
X
P55
HPLchg
EHPL
X
X
P54
VPLchg
EVPL
X
X
P53
HFchg
EHF
X
X
P52
VFchg
EVF
X
X
P51
FIFOI
EFIFO
X
X
P50
MI
EMI
VSYNC
EVSI
VSYNC
HSYNC
Digital Filter
Present
Vpre
Check
Frequency Vfreq
Count
Vself
CVSYNC
Polarity
Vpol
Check
VBpl
High
Frequency
Mask
Polarity Check &
Sync Seperator
Present
Check
CVpre
Hself
Hpol
HBpl
Digital Filter
Hpre
Present Check &
Frequency Count Hfreq
VBLANK
HBLANK
H/V SYNC Processor Block Diagram
PSTUS (r) : The status of polarity, presence and static level for HSYNC and VSYNC.
CVpre = 1 → The extracted CVSYNC is present.
= 0 → The extracted CVSYNC is not present.
Hpol = 1 → HSYNC input is positive polarity.
= 0 → HSYNC input is negative polarity.
Vpol = 1 → VSYNC (CVSYNC) is positive polarity.
= 0 → VSYNC (CVSYNC) is negative polarity.
Hpre = 1 → HSYNC input is present.
= 0 → HSYNC input is not present.
Vpre = 1 → VSYNC input is present.
= 0 → VSYNC input is not present.
Hoff* = 1 → HSYNC input's off-level is high.
= 0 → HSYNC input's off-level is low.
Voff* = 1 → VSYNC input's off-level is high.
= 0 → VSYNC input's off-level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) : H-Freq counter's high bits.
Hovf = 1 → H-Freq counter overflows; this bit is cleared by H/W when condition removed.
HF10 - HF8 : 3 high bits of H-Freq counter.
HCNTL (r) : H-Freq counter's low bits.
Revision 2.0
- 10 -
2001/05/18