PCA9547 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
PCA9547 Datasheet PDF : 26 Pages
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Philips Semiconductors
PCA9547
8-channel I2C-bus multiplexer with reset
11. Dynamic characteristics
Table 8.
Symbol
tPD
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tr
tf
Cb
tSP
tVD;DAT
tVD:ACK
RESET
tw(rst)L
trst
trec(rst)
Dynamic characteristics
Parameter
Conditions
Standard-mode Fast-mode I2C-bus Unit
I2C-bus
Min Max
Min
Max
propagation delay
from SDA to SDn,
or SCL to SCn
-
0.3[1]
-
0.3[1] ns
SCL clock frequency
0
100
0
400 kHz
bus free time between a STOP and
START condition
4.7
-
1.3
- µs
hold time (repeated) START condition
[2] 4.0
-
0.6
- µs
LOW period of the SCL clock
4.7
-
1.3
- µs
HIGH period of the SCL clock
4.0
-
0.6
- µs
set-up time for a repeated START
condition
4.7
-
0.6
- µs
set-up time for STOP condition
4.0
-
0.6
- µs
data hold time
0[3]
3.45
0[3]
0.9 µs
data set-up time
250
-
100
- ns
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
-
1000 20 + 0.1Cb[4] 300 ns
-
300 20 + 0.1Cb[4] 300 µs
-
400
-
400 µs
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50 ns
data valid time
HIGH-to-LOW
[5]
-
1
-
1 µs
LOW-to-HIGH
[5]
-
0.6
-
0.6 µs
data valid acknowledge time
-
1
-
1 µs
LOW-level reset time
reset time
reset recovery time
SDA clear
4
-
500
-
0
-
4
- ns
500
- ns
0
- ns
[1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
PCA9547_2
Product data sheet
Rev. 02 — 12 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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