CDS/ADC Timing Chart
N
CCDIN
CXD3406GA
N+1
N+2
N+3
XSHPI
XSHDI
ADCLKI
D0 to D9
N – 10
DL
N–9
tw1
N–8
N–7
∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
Symbol
tw1
DL
ADCLKI clock period
ADCLKI clock duty
Data latency
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Definition
Min. Typ. Max. Unit
54
50
9
ns
%
clocks
Preblanking Timing Chart
PBLKI
ADCLKI
D0 to D9
11 Clocks
11 Clocks
All "0"
– 16 –