ADF7020BCP View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF7020BCP Datasheet PDF : 40 Pages
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ADF7020
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB(6:15).
Bit Slicer
The received data is recovered by threshold detecting the output
of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).
Data Synchronizer
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the notes for the Register 3—Receiver Clock Register
section for a definition of how to program. The clock recovery
PLL can accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB(5:4)
should be set to [01]. To achieve best performance, the
bandwidth of the FSK correlator must be optimized for the
specific deviation frequency that is used by the FSK transmitter.
The discriminator BW is controlled in Register 6 by
R6_DB(4:13) and is defined as
Discriminator _ BW = (DEMOD _ CLK × K) /(800×103 )
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = Round(200e3/FSK Deviation)
Preliminary Technical Data
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
K
K/2
Even
Even
Even
Odd
R6_DB14
0
0
R6_DB29
0
1
Table 8. When K Is Odd
K
(K + 1)/2
Odd
Even
Odd
Odd
R6_DB14
1
1
R6_DB29
0
1
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB(6:15) and is given by
Post _ Demod _ BWSetting = 210 ×2π× FCUTOFF
DEMOD _ CLK
where FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter. This should typically be set to 0.75 times
the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
FDEV = 20 kHz
Therefore,
FCUTOFF = 0.75 × 9.6 × 103 Hz
Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz)
Post_Demod_BW = Round(9.26) = 9
and
K = Round(200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 =
63 (rounded to nearest integer)
Table 9.
Setting Name
Post_Demod_BW
Discriminator BW
Dot Product
Rx Data Invert
Register Address
R4_DB(6:15)
R6_DB(4:13)
R6_DB14
R6_DB29
Value
0x09
0x3F
0
0
Rev. PrH | Page 18 of 40
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