ADF7020BCP View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADF7020BCP

High Performance ISM Band FSK/ASK Transceiver IC

Analog Devices 

ADF7020

Preliminary Technical Data

Parameter

PLL Settling Time

REFERENCE INPUT

Crystal Reference

External Oscillator

Load capacitance

Input Level

TIMING INFORMATION

Chip Enabled to Regulator Ready

Crystal Oscillator Startup time

Tx to Rx Turnaround Time

LOGIC INPUTS

VINH, Input High Voltage

VINL, Input Low Voltage

IINH/IINL, Input Current

CIN, Input Capacitance

Control Clock Input

LOGIC OUTPUTS

VOH,Output High Voltage

VOL, Output Low Voltage

CLKOUT Rise/Fall

CLKOUT Load

TEMPERATURE RANGE—TA

POWER SUPPLIES

Voltage Supply

AVDD

DVDD

Transmit Current Consumption

−20 dBm

−10 dBm

0 dBm

10 dBm

Receive Current Consumption

Low Current Mode

High Sensitivity Mode

Power-Down Mode

Low Power Sleep Mode

Min

Typ

40

3.625

3.625

TBD

1

350 µs +

(5 × TBIT)

0.7 × V DD

DVDD −

0.4

−40

Max

Unit

µs

24

MHz

24

MHz

pF

CMOS

levels

TBD

µs

ms

V

0.2 × V DD V

±1

µA

10

pF

50

MHz

V

0.4

V

5

ns

10

pF

+85

°C

Test Conditions

Measured for a 10 MHz frequency step to

within 5 ppm accuracy,

PFD = 20 MHz, LBW = TBD

See the Reference Input Section

CREG = 100 nF

With 19.2 MHz XTAL

Time to synchronized data, includes AGC

settling

IOH = 500 µA

IOL = 500 µA

2.3

AVDD

TBD

12

15

22

19

21

0.1

3.6

V

AVDD

mA

mA

mA

mA

TBD

mA

TBD

mA

1

µA

FRF = 915 MHz, VDD = 3.0 V, PA is matched

in to 50 Ω

VCO_BIAS_SETTING = 3

1 Higher data rates are achievable depending on local regulations.

2 For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.

3 For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.

4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.

5 For matching details, see the LNA/PA Matching section.

6 See Table 5 for description of different receiver modes.

7 See Table 5 for description of different receiver modes.

8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

9 See the Image Rejection Calibration section.

Rev. PrH | Page 6 of 40

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