AD722 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD722 Datasheet PDF : 12 Pages
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AD722
PIN DESCRIPTIONS
Pin
Mnemonic
Description
1
STND
A Logical HIGH input selects NTSC encoding.
A Logical LOW input selects PAL encoding.
CMOS Logic Levels.
2
AGND
Analog Ground Connection.
3
FIN
FSC clock or parallel-resonant crystal, or 4FSC clock input.
For NTSC: 3.579 545 MHz or 14.318 180 MHz.
For PAL: 4.433 619 MHz or 17.734 480 MHz.
CMOS Logic Levels for subcarrier clocks.
4
APOS
Analog Positive Supply (+5 V ± 5%).
5
ENCD
A Logical HIGH input enables the encode function.
A Logical LOW input powers down chip when not in use.
CMOS Logic Levels.
6
RIN
Red Component Video Input.
0 to 714 mV for NTSC; 0 to 700 mV for PAL.
7
GIN
Green Component Video Input.
0 to 714 mV for NTSC.
0 to 700 mV for PAL.
8
BIN
Blue Component Video Input.
0 to 714 mV for NTSC.
0 to 700 mV for PAL.
9
CRMA
Chrominance Output (Subcarrier Only).*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
10
COMP
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
11
LUMA
Luminance plus SYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
12
SELECT
A Logical LOW input selects the FSC operating mode.
A Logical HIGH input selects the 4FSC operating mode.
CMOS Logic Levels.
13
DGND
Digital Ground Connections.
14
DPOS
Digital Positive Supply (+5 V ± 5%) .
15
VSYNC
Vertical Sync Signal (if using external CSYNC set at +5 V).
16
HSYNC
Horizontal Sync Signal (or CSYNC signal).
*The Luminance, Chrominance, and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.
DPOS
1
5
12
15
16
Circuit A
APOS
6
7
8
4pF
TYP
VCLAMP
Circuit C
APOS
APOS
3
9
10
VBIAS
11
Circuit B
Equivalent Circuits
–4–
Circuit D
Equivalent Circuit
Circuit A
Circuit B
Circuit A
Circuit C
Circuit C
Circuit C
Circuit D
Circuit D
Circuit D
Circuit A
Circuit A
Circuit A
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