FM3104 View Datasheet(PDF) - Ramtron International Corporation
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FM3104 Datasheet PDF : 22 Pages
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However, an advantage of combining a clock
function with FRAM memory is that data is not lost
regardless of the backup power source.
When a battery is used as a backup source, VDD must
be applied prior to inserting the battery to prevent
battery drain. Once VDD is applied and a battery is
inserted, the current drain on the battery is
guaranteed to be less than IBAK(max).
Trickle Charger
To facilitate capacitor backup the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin
FM3104/16/64/256
will source approximately 4 µA until VBAK reaches
VDD or 3.75V whichever is less. In 3V systems, this
charges the capacitor to VDD without an external
diode and resistor charger. In 5V systems, it provides
the same convenience and also prevents the user from
exceeding the VBAK maximum voltage
specification.
! Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 KΩ series
resistor as a safety element.
512 Hz
W
32.768 kHz
crystal
Oscillator
Clock
Divider
1 Hz
Update
Logic
CF
Years
8 bits
Months
5 bits
Date
6 bits
Days
3 bits
Hours
6 bits
Minutes
7 bits
Seconds
7 bits
User Interface Registers
R
Figure 7. Real-Time Clock Core Block Diagram
Calibration
When the CAL bit in a register 00h is set to 1, the
clock enters calibration mode. In calibration mode,
the CAL/PFO output pin is dedicated to the
calibration function and the power fail output is
temporarily unavailable. Calibration operates by
applying a digital correction to the counter based on
the frequency error. In this mode, the CAL/PFO pin
is driven with a 512 Hz (nominal) square wave. Any
measured deviation from 512 Hz translates into a
timekeeping error. The user converts the measured
error in ppm and writes the appropriate correction
value to the calibration register. The correction
factors are listed in the table below. Positive ppm
errors require a negative adjustment that removes
pulses. Negative ppm errors require a positive
correction that adds pulses. Positive ppm adjustments
have the CALS (sign) bit set to 1, where as negative
ppm adjustments have CALS = 0. After calibration,
the clock will have a maximum error of ± 2.17 ppm
or ± 0.09 minutes per month at the calibrated
temperature.
The calibration setting is stored in FRAM so is not
lost should the backup source fail. It is accessed with
bits CAL.4-0 in register 01h. This value only can be
written when the CAL bit is set to a 1. To exit the
calibration mode, the user must clear the CAL bit to a
0. When the CAL bit is 0, the CAL/PFO pin will
revert to the power fail output function.
Calibration Adjustments
Positive Calibration for slow clocks: Calibration will achieve +/- 2.17 PPM after calibration
Measured Frequency Range
Error Range (PPM)
Min
Max
Min
Max
Program Calibration Register to:
0
512.0000
511.9989
0
2.17
000000
1
511.9989
511.9967
2.18
6.51
100001
2
511.9967
511.9944
6.52
10.85
100010
3
511.9944
511.9922
10.86
15.19
100011
4
511.9922
511.9900
15.20
19.53
100100
5
511.9900
511.9878
19.54
23.87
100101
6
511.9878
511.9856
23.88
28.21
100110
Rev 0.2
May 2003
Page 7 of 22
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