ALC202 View Datasheet(PDF) - Realtek Semiconductor
Part Name
Description
Manufacturer
ALC202 Datasheet PDF : 42 Pages
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ALC202/ALC202A
7.2.7 ATE Test Mode
To meet AC’97 rev2.2 specifications, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in test mode.
Parameter
Symbol
Minimum
Typical
Maximum
Units
Setup to trailing edge of RESET#
Tsetup2rst
15.0
-
(also applies to SYNC)
-
ns
Rising edge of RESET# to Hi-Z
Toff
-
delay
-
25.0
ns
ATE test mode timing diagram
7.2.8 AC-Link IO Pin Capacitance and Loading
Output Pin
BIT_CLK (must support ≥ 2
CODECs)
SDATA_IN
1 CODEC
55pF
47.5pF
2 CODEC
62.5pF
55pF
3 CODEC
75pF
60pF
7.2.9 SPDIF Output
SPDIF_OUT
Rise time/fall time
Duty cycle
Minimum
0
45
T(h)
50%
Typical
T(l)
Maximum
10
55
90%
10%
4 CODEC
85pF
62.5pF
Units
%
%
Notes:
T(r)
T(f)
Rise time = 100 * T(r)/ (T(l)+ T(h))%
Fall time = 100 * T(f)/ (T(l)+ T(h))%
Duty cycle = 100 * T(h)/ (T(l)+ T(h))%
7.2.10 BIT-CLK and SDATA-IN State
When RESET# is active, BIT-CLK and SDATA-IN must be floating. The ac-link signals are driven by another AC’97 on a CNR
board. This requirement is not mentioned in the AC’97 specifications Rev 2.1. Please refer to CNR (Communication Network
Riser) specifications Rev.1.0 pages 23~25 or AC’97 Rev.2.2 for detailed information.
2002/07/30
29
Rev.1.28
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