SST25VF020B-80-4I-SA View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
SST25VF020B-80-4I-SA Datasheet PDF : 35 Pages
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A Microchip Technology Company
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is completed or reached its highest unpro-
tected memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be
software protected against any memory Write (Program or Erase) operation. The Write-Status-Regis-
ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After
power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
prevents any further alteration of the BPL, BP1, and BP0 bits of the status register and BSP and TSP
of Status Register 1. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is
“Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 5: Software Status Register Block Protection FOR SST25VF020B1
Status Register Bit2
Protected Memory Address
Protection Level
BP1
BP0
2 Mbit
0
0
0
None
1 (1/4 Memory Array)
0
1
030000H-03FFFFH
1 (1/2 Memory Array)
1
0
020000H-03FFFFH
1 (Full Memory Array)
1
1
000000H-03FFFFH
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)
T5.0 1417
©2011 Silicon Storage Technology, Inc.
8
S71417-03-000
02/11
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